LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY ula1bit IS
PORT(
		AddSub, Cin, Op	:IN  STD_LOGIC;
		xi, yi		:IN  STD_LOGIC;
		Cout, res	:OUT STD_LOGIC); 
END ula1bit;

ARCHITECTURE logic OF ula1bit IS

SIGNAL Y : STD_LOGIC;

BEGIN
	-- Mux2to1: Se AddSub=1, converte para complemento de 2
	--			Se AddSub=0, mantem o valor
	WITH AddSub SELECT
	Y <= (NOT yi) WHEN '1',
		  yi WHEN OTHERS;
	-- Mux2to1: Se Op=0, efetua o AND
	--        : Se Op=1, efetua o ADD/SUB
	res <= xi AND Y WHEN Op = '0' ELSE xi XOR Y XOR Cin;	
	Cout <= '0' WHEN Op = '0' ELSE (xi AND Y)OR(Cin AND xi)OR(Cin AND Y);	
END logic;		